1. Field of the Invention
The present invention relates to semiconductor devices and manufacturing method thereof, and, more specifically, to a semiconductor device breakdown voltage of which can be increased, and to the method of manufacturing the same.
2. Description of the Background Art
Recently, high voltage integrated circuits (HVIC) including CMOS transistors, bipolar transistors, high voltage isolating structure as well as level shift function by high voltage devices have been much developed in order to realize lower cost of power control system, lower power consumption and down sizing while providing higher performance.
FIG. 37 is a cross section showing a structure of a conventional CMOS transistor.
Referring to FIG. 37, an n.sup.- epitaxial layer 10 is formed on a main surface of a p.sup.- semiconductor substrate 2. An n.sup.+ buried impurity region 8 is formed enclosed by p.sup.- semiconductor substrate 2 and n.sup.- epitaxial layer 10.
A CMOS transistor is formed on the surface of n.sup.- epitaxial layer 10 above n.sup.+ buried impurity region 8.
The CMOS transistor includes a p channel MOS transistor 28 and an n channel MOS transistor 38.
The p channel MOS transistor 28 includes a gate electrode 22 formed on the surface of n.sup.- epitaxial layer 10 with a gate insulating film 20 interposed, and source/drain regions 24 and 26 of p type impurity regions formed at positions sandwiching, from left and right, the gate electrode 22.
The n channel MOS transistor 38 includes a gate electrode 32 formed on the surface of n.sup.- epitaxial layer 10 with a gate insulating film 30 interposed therebetween, and source/drain regions 34 and 36 of n type impurity regions formed at positions sandwiching from left and right, the gate electrode 32 in a p.sup.- impurity region 12 formed in n.sup.- epitaxial layer 10.
At the surface of n.sup.- epitaxial layer 10, the CMOS transistor is surrounded by an element isolating oxide film 18.
In the n.sup.- epitaxial layer 10, an n.sup.+ collector wall 14 is provided to surround the CMOS transistor, which is in turn surrounded by a p type isolating region 16.
FIG. 38 is a schematic view showing a depletion layer generated in the semiconductor device of FIG. 37.
Referring to FIG. 38, assume that the potential of n.sup.+ buried impurity region 8 is made higher with respect to the semiconductor substrate 2.
At this time, a depletion layer is generated from the interface between p.sup.- semiconductor substrate 2 and n.sup.+ buried impurity region 8 and from the pn junction between p.sup.- semiconductor substrate 2 and n.sup.- epitaxial layer 10 over the hatch region.
The electric field in the semiconductor device with this depletion layer formed will be described with reference to FIGS. 39 to 41.
FIG. 39 is a perspective view of n.sup.+ buried impurity region 8 which is cut at the interface between p.sup.- semiconductor substrate 2 and n.sup.- epitaxial layer 10.
It is assumed that the impurity concentration has been sufficiently lowered to increase the breakdown voltage of the p.sup.- semiconductor substrate 2.
Referring to FIG. 38, the electric field in the direction (A-A' in the figure) perpendicular to the bottom surface of n.sup.+ buried impurity region 8 is constant in the region of p.sup.- semiconductor substrate 2, as shown by the dotted line in FIG. 40.
Meanwhile, the electric field at the corner portion (the direction of B-B' in FIG. 39) of n.sup.+ buried impurity region 8 shows the maximum value at the pn junction portion between n.sup.+ buried impurity region 8 and p.sup.- semiconductor substrate 2.
The internal electric field and the inclination of the electric field of n.sup.+ buried impurity region 8 and p.sup.- semiconductor substrate 2 are represented, in approximation, by the following equations (5) and (6). ##EQU1##
Here, it is assumed that the electric field at the pn junction interface at the corner portion of n.sup.+ buried impurity region 8 is constant.
In the above equations, Q represents the total of space charges on the side of n.sup.+ buried impurity region 8 where electric line of force passing through the hatch portion of FIG. 39 terminates, l' represents corner radius of n.sup.+ buried impurity region 8, and r' represents the depth of diffusion of n.sup.+ impurity region 3.
As can be seen from equations (5) and (6), at the corner portion, the electric field at the pn junction interface changes, and provides the maximum electric field at the interface of the pn junction.
Namely, the breakdown voltage of the semiconductor device as a whole is determined by this maximum value of the electric field.
FIG. 41 shows the relation between r' and the electric field.
FIG. 41 shows the change of the electric field E when r' is multiplied by .alpha. with the value of .beta.', which is l'/r'=.beta.', being changed to 0, 1 and 3, assuming that the value of the electric field E (x=r') is 1 when the size of l' in the perspective view of FIG. 39 is 0.
As can be seen from FIG. 41, when the value of .alpha. is set to 3 or more, the electric field can be suppressed to about 1/10 when .beta.'=0.
If the value of .alpha. is set to be 3 or more with the value of .beta.' being 1 or 3, the electric field can be further suppressed. In other words, by setting the value of .alpha. to 3 or more, that is, by increasing the depth of diffusion of n.sup.+ buried impurity region 8, the electric field generated in the semiconductor device can be suppressed to be small, and therefore a semiconductor device having high breakdown voltage can be provided.
However, when the depth of diffusion of n.sup.+ buried impurity region 8 is increased, the diffusion in the lateral direction also increases.
For example, referring to FIGS. 42 and 43, an isolation region per one npn transistor of a class having the breakdown voltage of about 30 V requires the area of EQU (16 .mu.m+25 .mu.m.times.2) (40 .mu.m+25 .mu.m.times.2)=5940 .mu.m.sup.2.
When the distance X.sub.j of n.sup.+ buried impurity region 8 is tripled from 5 .mu.m to 15 .mu.m, it requires expansion of the size in the lateral direction of 10 .mu.m.
Therefore, the isolation region would be EQU (16 .mu.m+(25 .mu.m+10 .mu.m).times.2).times.(40 .mu.m+(25 .mu.m+10 .mu.m).times.2) =9460 .mu.m.sup.2,
and therefore the area of the isolating region per one npn transistor would be increased by about EQU (9460/5940).times.100=159.3%.
This increase of the area is against the recent demand of miniaturizing the semiconductor devices, and therefore the increase of the depth of diffusion of the n.sup.+ buried impurity region cannot be adopted as a method of suppressing the electric field.